1. Field of the Invention
This invention relates to a layout structure of a semiconductor integrated circuit formed by using a photolithographic process, a method of forming the layout structure, and a photomask for use in the photolithographic process to form the layout structure.
2. Description of the Related Art
Semiconductor memory integrated circuits such as RAM (Random Access Memory), ROM (Read Only Memory), or the like, generally have a memory cell array and various kinds of peripheral circuits arranged around the memory cell array. In the memory cell array, a specific number of memory cells, each of which is a unit for storing information, are generally two-dimensionally arranged. The peripheral circuits read and write information from and to the desired memory cells within the memory cell array.
In such semiconductor memory, which includes the memory cell array and the peripheral circuits, peripheral circuit regions are formed by one-dimensionally arranging a number of various types of “peripheral circuit cells”, along the corresponding sides of the memory-cell array. Each of the peripheral circuit cells includes a device pattern for forming a circuit for interfacing with a corresponding number (usually, 1, 2, 4, 8, 16, . . . , 2n; wherein n is an integer not less than zero) of rows or columns of the memory cell array.
In general, the process margin is constantly decreasing with the rapid advance of fine patterning used for manufacturing semiconductor integrated circuits. In particular, while processing in an area where the patterns having the same dimension are arranged with a uniform density can be made with relative ease, it is generally extremely difficult to make processing with sufficient precision in an area where the patterns have low uniformity.
When an exposing light irradiates a semiconductor substrate having a positive-type photo resist layer through a patterned mask, ideally, the exposing light does not irradiate the area where the mask pattern is provided. Therefore, the resist layer on these masked areas is not exposed.
However, in reality, some of the exposing light reaches the area on the semiconductor substrate where the patterned mask is provided, due to scattering of the exposing light passing through the space between the mask patterns. As a result, the resist in the area, which is not to be exposed, is partially exposed. With the decrease of the pattern dimension, such unintended exposure of the resist layer becomes a significant problem.
Even in such a situation, the region having high uniformity of pattern density and high pattern regularity, such as, for example, the inner region of the memory cell array, can be processed with sufficient precision. That is, correction of the mask pattern by giving consideration to the resist pattern deformations due to the scattered light, or an optical proximity correction (OPC), can be effectively performed on a region having high uniformity of pattern density and high pattern regularity. In addition, the optimization of exposing conditions may also be effective for such a region.
However, at the outermost portion of the memory cell array, the pattern regularity is lost and the uniformity of pattern density is markedly degraded. As a result, the processing at the outermost portion of the memory cell array often leads to an insufficient precision.
Accordingly, a conventional method has been made in which “dummy cells” having the same pattern as the memory cell, and which are not required for realizing logical functions of the semiconductor integrated circuit, are arranged along the outer perimeter of the memory cell array. Thereby, the pattern density around the outer perimeter of the memory cell array is improved. See Japanese Unexamined Patent Application Publication No. 61-214559 (Patent Document 1), which is incorporated herein by reference.
As described above, for the memory cell array in which a plurality of cells, each having the same device pattern, the uniformity of pattern density can be improved by arranging dummy cells having the same pattern as the cells. On the other hand, for a semiconductor integrated circuit having various device patterns for providing various logical functions, a technique has been proposed in which dummy patterns different from the device pattern are arranged in the region with low pattern density, i.e., the region having no device pattern. See Japanese Unexamined Patent Application Publication No. 2002-9161 (Patent Document 2), which is also incorporated herein by reference.
According to the technique disclosed in Patent Document 2, two data are separately created on a CAD tool. The first one is a data in which the dummy pattern cells, each having a dummy pattern, are arranged over the entire chip area where the device structures of the semiconductor integrated circuit is to be formed. The second one is a data in which device patterns for realizing logical functions of the semiconductor integrated circuit, such as active region patterns, well patterns, gate electrode patterns, and the like, are arranged in the same chip area. Subsequently, these two data of the chip area are superimposed by logical synthesis, whereby a data of the chip area, in which both of the device patterns and the dummy cells are arranged, is created. It should be noted that, in the logical synthesis, the dummy cells that overlap the device patterns are deleted. In general, on the chip area thus designed, the dummy cells are arranged so as to surround the device patterns.
However, according to the technique disclosed in Patent Document 1, no measure is provided for improving the uniformity of pattern density in the peripheral circuit region, leading to marked irregularities in the pattern density at the perimeter of the peripheral circuit region, thus often resulting in pattern formation with insufficient precision.
Furthermore, each peripheral circuit cell has a large area as compared with the memory cell. Therefore, a simple application of the technique disclosed in Patent Document 1, i.e., arranging dummy cells each having the same device pattern as with the peripheral circuit cell around the perimeter of the peripheral circuit region, would require an excessively large waste of the area on the chip.
It would be also possible to employ the technique disclosed in Patent Document 2 for improving the uniformity of pattern density at the perimeter of the peripheral circuit region.
However, in the technique disclosed in Patent Document 2, there is a need to maintain a margin between the dummy pattern and the device pattern for ensuring adequate electrical insulation between the two patterns and for accounting for the error in the mask alignment. Accordingly, dummy cells are deleted over a region larger than the region where the device patterns are arranged by a certain margin. This procedure leads to the creation of gaps between the device patterns and the dummy cells.
Furthermore, there is no relationship between the layout of the dummy cells and the layout of the device pattern. That is, there is no relationship between the grids used in the CAD tool on which the dummy cells are placed and the grids on which the device patterns are placed. Accordingly, the size of the gap between the device pattern and the dummy cell remaining after they are superimposed on each other differs for each device pattern.
Accordingly, even if the dummy pattern arranging technique disclosed in Patent Document 2 is applied to arrange dummy cells around the perimeter of the peripheral circuit region, gaps with varying sizes will form between the device patterns at the outermost portion of the peripheral circuit region and the dummy patterns. With such a layout, while the uniformity of the pattern density is improved compared to a layout having no dummy patterns, the uniformity is not sufficiently improved for advanced fine-patterning technology.
Furthermore, the dummy pattern layout technique disclosed in Patent Document 2 was proposed to improve the uniformity of pattern density, not to improve the pattern regularity.
In many cases, the peripheral circuit region includes at least one layer in which a plurality of line-shaped patterns are arranged in parallel with each another with generally the same interval, whereby a line-and-space repetition structure is formed along a certain direction. The inventor has discovered through experiments that the exposure process is affected by the pattern regularity formed by such repetition structure, as well as by the uniformity of pattern density. Especially, when forming fine patterns with a width of half or less than the wavelength of the exposing light of 248 nm or less, the process is greatly affected by pattern regularity.
However, the exemplary dummy pattern disclosed in Patent Document 2 has the shape of a simple rectangle. Such dummy pattern would not provide the pattern regularity of the same level of regularity at the internal portion of the peripheral circuit region. Accordingly, even if the dummy pattern layout technique disclosed in Patent Document 2 improves the uniformity of pattern density, this technique does not improve the pattern regularity.
Accordingly, even if the dummy pattern arranging technique disclosed in Patent Document 2 is applied to the peripheral circuit region, significant pattern deformations would occur at the outermost portion of the peripheral circuit region due to poor uniformity of pattern density and poor pattern regularity. Thus, it becomes difficult to perform processing with the high precision required for advanced fine-patterning technology in the future.
It should be appreciated that an extensive OPC may be made so as to correct the significant deformation of the pattern occurring at the region where the pattern is formed with low uniformity and regularity. However, such extensive correction generally leads to a reduction of process margin, that is, the resist pattern becomes susceptible to significant dimensional deviation due to deviation in the exposing light intensity, the deviation of the focus, and the like, over the exposed area. As a result, the resist pattern is formed with extremely poor precision around the perimeter of the peripheral circuit region.
Furthermore, with the technique disclosed in Patent Document 2, logical synthesis processing, which requires a great deal of calculation, is required, leading to a long processing time for the layout design.